1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a word line driving circuit for a semiconductor memory device.
2. Background of the Related Art
As shown in FIG. 1, a word line driving circuit of a related art semiconductor memory shown in U.S. Pat. No. 4,951,259 to Sato et al. includes a predecoder PDCR that inputs addresses ax0, .sub.ax0, ax1, .sub.ax1 from an X address buffer XADB (not shown) and outputs signals .phi.x0, .phi.x1, .phi.x2 and .phi.x3. NAND gate circuits NAG0-NAGk input the addresses ax2, .sub.ax2, . . . , axi, .sub.axi from the X address buffer XADB (not shown) and output the signals .sub.S0, . . . , .sub.Sk. Switch transistors Q13-Q16 have gate terminals that receive the signals .phi.x0, .phi.x1, .phi.x2 and .phi.x3 output from the predecoder PDCR. The word line driving circuit further includes transistors Q23-Q26 that input a signal .phi.ce generated from a timing controller TC (not shown) at their gate terminals and X address decoder blocks WD0, WD3, . . . , WDm-3, WDm for driving the word lines W0-Wm.
FIG. 2 shows the word line driving circuit of FIG. 1 and its peripheral circuits, which include the timing controller TC, the X address buffer XADB and the X decoder XDCR. A memory cell array and corresponding bit line sense amplifier arrays are also shown in FIG. 2.
To drive the word line connected to the memory cell, the NAND gate circuits receive and NAND-decode the addresses ax2, .sub.ax2, . . . , axi, .sub.axi generated from the X address buffer XADB and the signal ce of logic high level generated from the timing controller TC and output the signals .sub.S0, . . . , .sub.Sk of logic low levels. In this case; one of the transistors Q13, Q14, Q15, Q16 shown in FIG. 1 is turned on by the one logic high signal of the signals .phi.x0, .phi.x1, .phi.x2 and .phi.x3 output from the predecoder PDCR. Thus, a transistor Qd1 in an X address decoder block XDCR is turned on to drive the corresponding word line for a predetermined time.
However, the related art word line driving circuit has various disadvantages. When the related art word line driving circuit is applied to a memory cell block having a plurality of word lines, the required word lines have greater loading, which increases the word line driver size. As the word line driver size increases, the size of the address decoding block and the size of precharge transistor increase. Consequentially, as large amount of currents is consumed at each operation, which increases the power consumption and deteriorates the operating speed.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.